Memory and FPGA

1.  A RAM is a Volatile and either Static or Dynamic Memory

2.  The density of Dynamic RAM is more than that of the Static RAM

Ans : 

• DRAM stores the binary information in the form of electric charges on capacitors
• The capacitor tends to discharge with time and must be periodically recharged by refreshing the dynamic memory.
• DRAM offers reduced power consumption and larger storage capacity in a single memory chip.
• High density, high capacity, low cost, low speed & low power consumption.

3. Which of the following memories can be programmed once by the user and then cannot be erased and reprogrammed?

Ans :

PROM – Programmable Read Only Memory. This memory can be programmed just once after manufacturing by "blowing" the fuses, which is an irreversible process.

4.  A 12-bit Hamming code word containing 8 bit of data and 4 parity bits is read from memory. What was the original 8-bit data word that was written into the memory if the 12-bit word read out is (101111110100)2

Ans:

Hamming code K parity bit in n data bit. Parity bits are positioned in powers of 2.

For 4 parity bit (P) and 8 data bit (D)

For the codeword (101111110100)2

P1 à1,    P2à0  , P4à1 ,  P8à1

Data : 11110100

5. How many parity check bits must be included in the data word to achieve single-error correction and double-error detection when the data word contains 32-bits.

Ans: 7

6. Given the 8-bit data word 01011011, generate the 13-bit composite word for the Hamming code that corrects the single errors and detect double errors.

P1à XOR(3,5,7,9,11) àXOR(0,1,1,1,1)à0

P2à XOR(3,6,7,10,11) àXOR(0,0,1,0,1)à0

P4à XOR(5,6,7,12) àXOR(1,0,1,1)à1

P8à XOR(9,10,11,12) àXOR(1,0,1,1)à1

13th bit XOR (000110111011) = 1

Therefore, the 13-bit Hamming Code that corrects single error and detects double errors is

0001 1011 1011 1

7. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input-output data lines are needed respectively for 16M * 32.

Ans:

16M x 32,  16M = 16 × 2²⁰ = 2⁴X2²⁰, so 16M x 32 takes 24 address lines and 32 data lines

8. For the given circuit which of the following are correct

Ans:

Enable – 0 (Active low)

R/ W'= 0 à Write

So, Decimal 10 is written into the memory location 211.

9. How many address and data lines is there in 1M X 16 ROM system?

Ans :  20 and 16 as 2²⁰ gives 1M. So 20 and 16.

10. Which of the following statement is false ?

Ans : The access time of a sequential memory is constant independent of the position of the word.

11.What function is implemented at the output Q of the following PAL structure?

Ans : 

BC’

The given structure as the OR Array is fixed with 4.

12. How many 4-input LUTs would be required in an FPGA to implement the function Y=AB+C’?

Ans : 1

Because 4-input LUTs can perform any combinational logic function of upto 4 inputs.

13. The number of ACT1FPGA logic Blocks needed to realize the 4-input logic function f(a,b,c,d) = ∑(0,1,2,5,8,9,10,13) is 

Ans : 1 as the input of the logic function is 4.

14. Between coarse- and fine-grained FPGA blocks 

Ans : 

All are valid,

·         Coarse-grained required more area

·         Coarse-grained can accommodate more logic

·         Coarse-grained have more average fanouts

     15. What is the minimum size ROM is required to implement an unsigned 4-bit binary adder?

      Ans :

       2 4-bit à 8-bit input lines, so 2⁸ = 256 , 5-bit output àC4 S3 S2 S1 S0 ( 1à output carry, 4 à Sum bit)

So, ROM size = 256X5