1. The advantage of using a dual slope ADC in a digital voltmeter is that high Accuracy
Answer :
The dual-slope ADC
architecture was truly a breakthrough in ADCs for high resolution and high accuracy applications
such as digital voltmeters (DVMs), etc.
2. The
fastest ADC is Flash
type.
3. Which ADC has fixed Conversion time ?
Answer :
Successive Approximation as SAR the conversion time is
independent of the magnitude of the input sampled value.
4. Find
the full scale output of a 4-bit DAC produce an output of 0.1V for a digital input 0001.
Answer : 1.5V
5. What is the output of the following circuit for
the input b4=1, b3=0, b2=1, b0=0 and Vref =16V ?
Answer : -5V
6. Output
of the Mealy machine depends on both present input and present state .
7. Compared to Moore FSM , a mealy FSM might have fewer states and have output generally one
clock cycle earlier.
8. The number of comparators in a 4-bit flash ADC
is 15
Answer :
As the number of comparators is given by
2N-1, 16-1 =15
9. Consider the circuit shown below . What
would be the output sequence Z whne the input sequence x=01100. Assume the
initial state {AB} = {00}
Answer :
JA = ((x’B)’(xB’)’)’ =
x’B+xB’
KA = x’B
JB = (x’+A’)’ = xA
KB = (x’+A’)’ = xA
Z = (A’+B’)’ = AB
Output Sequence Z = 00101
10. Let
X is the input sequence whereas Z is the output sequence for the state machine
given below . Which of the following option correctly describes the output Z
sequence for the input sequence X given below.
X = 001101101011010
Answer :
Initial state à
S0
·
When the input X is 0, the state moves from S0àS2
and the output is 0
·
X = 0 , S2 à
S2 , Z=0
·
X = 1, S2 à S4, Z = 0
·
X = 1, S4 à S3, Z= 1 ……….
The output Sequence Z = 00010110100101
11. An 8-bit DAC has Vref = -5V. What is the output voltage when
Bin = 10110100? (Assume Rf = R/2)
Answer :
The output voltage is 3.516 V
12. ___________ in DACis defined as variation in analog step
sizes between successive bits.
Answer :
Differential Non-Linearity
Error :
Analog step size changes with increasing digital input, measure of largest
deviation between successive bits.
13. The figure below shows a 3-bit Flash ADC
circuit. What would be the encoded binary output D { D2D1D0}when
V=8V and Vin = 3.45V
Answer :
Procedure : Set the MSB of the Digit as 1 and evaluate
the VDAC and compare with Vin.
·
If
Vin > VDAC , SAR
bit is unchanged
·
If
Vin < VDAC , SAR
bit is Reset.
Ø 3-Bit
ADC ,Vin = 3.45, Vref = 8
Ø SAR
= 100
VDAC
= Vref/2^1 = 8/2 = 4 , Vin < VDAC , SAR bit 3 is reset , 000
Ø SAR
= 010
VDAC
= 0+Vref/2^2 = 0+8/4 = 2 , Vin > VDAC , SAR bit 2 is unchanged , 010
Ø SAR
= 011
VDAC
= 0+2+Vref/2^3 = 0+2+ 8/8 = 3 , Vin >
VDAC , SAR bit 1 is unchanged , 011
The answer is 011.
13. In
a 5-bit successive approximation ADC with the reference voltage 1V, If an input
voltage of 0.67V is applied , after 3 clock cycles the content of SAR is
Answer :
Ø 5-Bit
ADC ,Vin = 0.67, Vref = 1
Ø SAR
= 10000 (First cycle)
VDAC
= Vref/2^1 = 1/2 = 0.5 , Vin > VDAC , SAR bit 5 is unchaged , 10000
Ø SAR
= 11000 (Second Cycle)
VDAC
= 0.5+Vref/2^2 = 0.5+1/4 = 0.75 , Vin
< VDAC , SAR bit 4 is reset , 10000
Ø SAR
= 10100 (Third Cycle)
VDAC
= 0.5+0+Vref/2^3 = 0.5+0+1/8 =0.625 ,
Vin > VDAC , SAR bit
3 is unchanged , 10100
The answer , after 3 clock cycle
the content of SAR is 10100
15. In
a 5-bit successive approximation ADC with the reference voltage 1V, If an input
voltage of 0.3V is applied , after 4 clock cycles the content of SAR is
Answer :
Ø 5-Bit
ADC ,Vin = 0.3, Vref = 1
Ø SAR
= 10000 (First cycle)
VDAC
= Vref/2^1 = 1/2 = 0.5 , Vin < VDAC , SAR bit 5 is reset , 00000
Ø SAR
= 01000 (Second Cycle)
VDAC
= 0+Vref/2^2 = 0+1/4 = 0.25 , Vin > VDAC , SAR bit 4
is unchanged , 01000
Ø SAR
= 01100 (Third Cycle)
VDAC
= 0+0.25+Vref/2^3 = 0+0.25+1/8 =0.325 ,
Vin < VDAC , SAR bit
3 is reset , 01000
Ø SAR
= 01010 (Third Cycle)
VDAC
= 0+0.25+0+Vref/2^4 = 0+0.25+0+1/16 =0.3125
, Vin < VDAC , SAR
bit 2 is reset , 01000
The answer , after 3 clock cycle
the content of SAR is 01000
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