1. How many flip flop will be complemented in a 10 bit binary up counter to reach the next count after the count 1001100111.
Answer :
Add 1 to the value and see the number of bits get toggled
to obtain the number of flip flop need
to be complemented in a binary up counter to reach the next count
4 bits are toggled
to obtain next count . So, 4 flip flops
will be complemented.
2. A binary ripple counter uses flip-flops that trigger on the positive edge of the clock. What will be the count if the normal outputs of the flip-flops are connected to the clock input of the next stage.
Answer : Positive Triggering : 0 à1 , flip flop toggles when the clock goes 0 à1
A count down counter
3. The contents of a four-bit register are initially 0110. The register is shifted six times to the right with the serial input being 1011100 ( inputs are applied from right to left ). What is the content of the register after each shift ?
Answer :
Content of the
register : 0110
Input : 1011100
Output : 0011 ; 0001; 1000 ; 1100; 1111; 0111; 1011
4. The
characteristic equation of SR flip flop is Q(n+1)
= S+R’Qn
5. A 4 bit shift
register circuit configured for right shift operation ( Din àA, AàB,
B à C, CàD) as shown. If present state of the shift register
is ABCD = 1101, the number of the clock cycles required to reach the state ABCD
0100 is
Answer :
Present state : 1101 ,
Din is A ⊕ D
output : 0100
6. The race around
condition occurs in a J-K flip flop when
Answer :
JK
flipflop has three inputs and two outputs. Outputs are complementary to each
other.
when J =K = 0 and clk = 1; output of AND gates will be 0; when any one input of NOR gate is 0 output of NOR gate will be complement of other input, so output remains as previous output.
when J =0 K =1 and clk = 1; output of AND gate connected to K will be Q and corresponding NOR gate output will be 0; which RESETs the flipflop.
when J =1 K = 0 and clk = 1; output of AND gate connected to j will be Q' and corresponding NOR gate output will be 0; which the SETs the flipflop.
when J =1 K = 1 and clk = 1; Q output will toggle as long as CLK is high. Thus the output will be unstable creating a race-around problem with this basic JK circuit.
when J =K = 0 and clk = 1; output of AND gates will be 0; when any one input of NOR gate is 0 output of NOR gate will be complement of other input, so output remains as previous output.
when J =0 K =1 and clk = 1; output of AND gate connected to K will be Q and corresponding NOR gate output will be 0; which RESETs the flipflop.
when J =1 K = 0 and clk = 1; output of AND gate connected to j will be Q' and corresponding NOR gate output will be 0; which the SETs the flipflop.
when J =1 K = 1 and clk = 1; Q output will toggle as long as CLK is high. Thus the output will be unstable creating a race-around problem with this basic JK circuit.
7. The minimum
number of flip flops required to design a MOD-10 ripple counter is 4
Answer : MOD 10 à 10 binary value 1010 so 4 flip flops.
8. In general ,a
sequential logic circuit consist of flip-flops and combinational circuits.
Answer : A sequential logic circuit consists of a
combinational circuit and memory elements that form a feedback system. Flip
flop used as memory element.
9. While converting JK flip-flop to D Flip-flop, instead of
connecting an invertor between J and K inputs a buffer has been connected . The
resulting circuit will be T
Flip-flop
10. Between a Latch
and Flip-flop which one has higher possibility of getting input data noise
propagated to it output.
Answer : Latch act faster
than the flip-flop as it react immediately once the input change.
11. A Finite State
Machine (FSM) with one input (X) and one output (Z) is defined by the state
diagram below . Assume FSM starts with the state A. Given is the following
sequence of input (X) values.
X :
10010110101010.
What state is the FSM in at the end of the above sequence ?
What input can be detected by this ?
Answer : State C , Sequence detected 101
12. What is the
function implemented by the circuit given below ? Assume the signal w is driven
by square wave signal.
Answer :
When both
flip-flops are cleared, their outputs are Q0 = Q1 = 0. After the Clear input
goes high, each pulse on the w input will cause a change in the flip-flops as
indicated in Figure. Note that the figure shows the state of the signals after
the changes caused by the rising edge of a pulse have taken place. In
consecutive time intervals the values of Q1Q0 are 00, 01, 10, 00, 01, and so on.
Therefore, the circuit generates the counting sequence: 0, 1, 2, 0, 1, and so
on. Hence, the circuit is a modulo-3 counter.
13.What would be
the number of flip-flops required to design mod-10 ring counter and mod-10
Johnson counter respectively?
Answer :
To design MOD-N
ring counter , N number of flip-flop is needed., so, 10 flip-flops are needed.
The MOD of the Johnson counter is 2n if n flip-flops are used. So, if MOD-10 counter is to be designed 10
can be written as 2n = 2X5, 5 flip-flop
is needed.
14.What is the
modulus of the counter circuit shown below ?
Answer : MOD – 10 counter
15.What logic block
should be placed at the point X so that circuit acts as a MOD-7 counter?
Answer :
X should be
replaced by Three input NAND gate ,
so that the ripple counter can be reset for 7 (111).
No comments:
Post a Comment