Platform to Learn: Decoders and Sequential Circuits

Decoders and Sequential Circuits

1. Combinational logic Circuit contains only logic gates, sequential logic circuit contains flip-flop.

2. A flip-flop has two output which are always complimentary.

3. A flip-flop can be designed using NAND,NOR and basic gates.

4. Which of the following combination is not allowed in an SR flip-flop?

S=1 , R=1 is indeterminant

5.The following circuit implements

Ans : In XOR , if one input is 0 (A) the output is same as that of the other input (B)

if one input is 1 (A) the output is complement of the other input (B)

If Q=0, Value given in T will the output , If Q=1, complement of the value given in T will be the output. So, it implements T flip flop.

6. The output Q_n of J-K (S-R) flip flop is ‘0’. It’s output does not change when a clock pulse is applied. The inputs J_n and K_n(S, and Rn) are respectively ‘0’ and ‘x’.

7. The JK flip flop shown below is initially cleared and then clocked for 5 pulses, the sequence at the Q output will be

Answer :

Q(n+1) is the output (Next state)

Q is the present state

J is the complement of previous Q(n+1)

Ans : Q = 010101

8. PLA – Programmable Logic Array consist of AND & OR arrays

9. . A Latch is an example of a Bistable multivibrator because a Bistable multivibrator is one in which the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-versa.

10. Identify the circuits shown in the figure.

Positive edge triggered D flip flop where X is input , Y is clock and Q is output.

Each mux input select is driven from the CLK signal but uses a different CLK polarity. The first mux latches when Y=0, the second latches when Y=1. So it is called as Positive edge triggered

For negative edge triggered , first Mux latches when Y=1, the second latches when Y=0.

11. An SR latch is created using only two NOR gates with S and R inputs feeding on NOR gate each. If both S and R set to ‘1’, the outputs will be Q and Q’ is 0.

12. Serial inputs are applied in the following manner to JK flip flop through the AND gate as shown in the figure. What would be the resulting serial data that would be present at the output Q? There is one clock pulse for each bit time. Assume that Q is initially 0. Preset and Clear is always high. The inputs are always applied from left to right.