Memory and FPGA

1.  A RAM is a Volatile and either Static or Dynamic Memory

2.  The density of Dynamic RAM is more than that of the Static RAM

Ans : 

• DRAM stores the binary information in the form of electric charges on capacitors
• The capacitor tends to discharge with time and must be periodically recharged by refreshing the dynamic memory.
• DRAM offers reduced power consumption and larger storage capacity in a single memory chip.
• High density, high capacity, low cost, low speed & low power consumption.

3. Which of the following memories can be programmed once by the user and then cannot be erased and reprogrammed?

Ans :

PROM – Programmable Read Only Memory. This memory can be programmed just once after manufacturing by "blowing" the fuses, which is an irreversible process.

4.  A 12-bit Hamming code word containing 8 bit of data and 4 parity bits is read from memory. What was the original 8-bit data word that was written into the memory if the 12-bit word read out is (101111110100)2

Ans:

Hamming code K parity bit in n data bit. Parity bits are positioned in powers of 2.

For 4 parity bit (P) and 8 data bit (D)

For the codeword (101111110100)2

P1 à1,    P2à0  , P4à1 ,  P8à1

Data : 11110100

5. How many parity check bits must be included in the data word to achieve single-error correction and double-error detection when the data word contains 32-bits.

Ans: 7

6. Given the 8-bit data word 01011011, generate the 13-bit composite word for the Hamming code that corrects the single errors and detect double errors.

P1à XOR(3,5,7,9,11) àXOR(0,1,1,1,1)à0

P2à XOR(3,6,7,10,11) àXOR(0,0,1,0,1)à0

P4à XOR(5,6,7,12) àXOR(1,0,1,1)à1

P8à XOR(9,10,11,12) àXOR(1,0,1,1)à1

13th bit XOR (000110111011) = 1

Therefore, the 13-bit Hamming Code that corrects single error and detects double errors is

0001 1011 1011 1

7. The memory units that follow are specified by the number of words times the number of bits per word. How many address lines and input-output data lines are needed respectively for 16M * 32.

Ans:

16M x 32,  16M = 16 × 2²⁰ = 2⁴X2²⁰, so 16M x 32 takes 24 address lines and 32 data lines

8. For the given circuit which of the following are correct

Ans:

Enable – 0 (Active low)

R/ W'= 0 à Write

So, Decimal 10 is written into the memory location 211.

9. How many address and data lines is there in 1M X 16 ROM system?

Ans :  20 and 16 as 2²⁰ gives 1M. So 20 and 16.

10. Which of the following statement is false ?

Ans : The access time of a sequential memory is constant independent of the position of the word.

11.What function is implemented at the output Q of the following PAL structure?

Ans : 

BC’

The given structure as the OR Array is fixed with 4.

12. How many 4-input LUTs would be required in an FPGA to implement the function Y=AB+C’?

Ans : 1

Because 4-input LUTs can perform any combinational logic function of upto 4 inputs.

13. The number of ACT1FPGA logic Blocks needed to realize the 4-input logic function f(a,b,c,d) = ∑(0,1,2,5,8,9,10,13) is 

Ans : 1 as the input of the logic function is 4.

14. Between coarse- and fine-grained FPGA blocks 

Ans : 

All are valid,

·         Coarse-grained required more area

·         Coarse-grained can accommodate more logic

·         Coarse-grained have more average fanouts

     15. What is the minimum size ROM is required to implement an unsigned 4-bit binary adder?

      Ans :

       2 4-bit à 8-bit input lines, so 2⁸ = 256 , 5-bit output àC4 S3 S2 S1 S0 ( 1à output carry, 4 à Sum bit)

So, ROM size = 256X5 

Finite State Machine and Data Converters (ADC & DAC)

 1. The advantage of using a dual slope ADC in a digital voltmeter is that high Accuracy

Answer : 

The dual-slope ADC architecture was truly a breakthrough in ADCs for high resolution and high accuracy applications such as digital voltmeters (DVMs), etc. 

2.  The fastest ADC is  Flash type.

3. Which ADC has fixed Conversion time ?

Answer :

Successive  Approximation as SAR the conversion time is independent of the magnitude of the input sampled value.

     

      4.  Find the full scale output of a 4-bit DAC produce an output of  0.1V for a digital input 0001.  

      Answer : 1.5V 

      5. What is the output of the following circuit for the input b4=1, b3=0, b2=1, b0=0 and Vref =16V ?  

         

  

      Answer : -5V 

6. Output of the Mealy machine depends on  both present input and present state .

7. Compared to Moore FSM , a mealy FSM might have fewer states and have output generally one clock cycle earlier.

8. The number of comparators in a 4-bit flash ADC is 15

Answer :

 As the number of comparators is given by 2^N-1, 16-1 =15

      9. Consider the circuit shown below . What would be the output sequence Z whne the input sequence x=01100. Assume the initial state {AB} = {00}

      

         Answer :

         J_A = ((x’B)’(xB’)’)’ = x’B+xB’

   K_A = x’B

   J_B = (x’+A’)’ = xA

   K_B = (x’+A’)’ = xA

   Z = (A’+B’)’ = AB

Output Sequence Z = 00101

10.  Let X is the input sequence whereas Z is the output sequence for the state machine given below . Which of the following option correctly describes the output Z sequence for the input sequence X given below.

X = 001101101011010 

Answer :

 Initial state à S0

·         When the input X  is 0, the state moves from S0àS2 and the output is 0

·         X = 0 , S2 à S2 , Z=0

·         X = 1, S2 à S4, Z = 0

·         X = 1, S4 à S3, Z= 1 ……….

The output Sequence Z = 00010110100101

     11. An 8-bit DAC has V_ref  = -5V. What is the output voltage when B_in = 10110100? (Assume Rf = R/2)

      Answer :

         

        The output voltage is 3.516 V

     12. ___________ in  DACis defined as variation in analog step sizes between successive bits.

      Answer :

      Differential Non-Linearity Error : Analog step size changes with increasing digital input, measure of largest deviation between successive bits.

    13. The figure below shows a 3-bit Flash ADC circuit. What would be the encoded binary output D { D₂D₁D₀}when V=8V and Vin = 3.45V

        Answer :

         Procedure :  Set the MSB of the Digit as 1 and evaluate the V_DAC and compare with Vin.

·         If  Vin > V_DAC     , SAR bit  is unchanged

·         If  Vin < V_DAC     , SAR bit is Reset.

Ø  3-Bit ADC ,Vin = 3.45, Vref = 8 

Ø  SAR = 100   

V_DAC = Vref/2^1 = 8/2 = 4  , Vin < V_DAC     , SAR bit 3  is reset , 000

Ø  SAR = 010   

V_DAC = 0+Vref/2^2 = 0+8/4 = 2  , Vin > V_DAC     , SAR bit 2  is unchanged , 010

Ø  SAR = 011   

V_DAC = 0+2+Vref/2^3 = 0+2+ 8/8 = 3  , Vin > V_DAC  , SAR bit 1  is unchanged , 011

The answer is 011.

13. In a 5-bit successive approximation ADC with the reference voltage 1V, If an input voltage of 0.67V is applied , after 3 clock cycles the content of SAR is 

Answer :

Ø  5-Bit ADC ,Vin = 0.67, Vref = 1

Ø  SAR = 10000 (First cycle)   

V_DAC = Vref/2^1 = 1/2 = 0.5  , Vin > V_DAC     , SAR bit 5  is unchaged , 10000

Ø  SAR = 11000   (Second Cycle)

V_DAC = 0.5+Vref/2^2 = 0.5+1/4 = 0.75  , Vin < V_DAC  , SAR bit 4  is reset , 10000

Ø  SAR = 10100    (Third Cycle)

V_DAC = 0.5+0+Vref/2^3 = 0.5+0+1/8 =0.625  , Vin > V_DAC  , SAR bit 3  is unchanged , 10100

The answer , after 3 clock cycle the content of SAR is 10100

15. In a 5-bit successive approximation ADC with the reference voltage 1V, If an input voltage of 0.3V is applied , after 4 clock cycles the content of SAR is 

Answer :

Ø  5-Bit ADC ,Vin = 0.3, Vref = 1

Ø  SAR = 10000 (First cycle)   

V_DAC = Vref/2^1 = 1/2 = 0.5  , Vin < V_DAC     , SAR bit 5  is reset , 00000

Ø  SAR = 01000   (Second Cycle)

V_DAC = 0+Vref/2^2 = 0+1/4 = 0.25  , Vin > V_DAC  , SAR bit 4  is unchanged , 01000

Ø  SAR = 01100    (Third Cycle)

V_DAC = 0+0.25+Vref/2^3 = 0+0.25+1/8 =0.325  , Vin < V_DAC  , SAR bit 3  is reset , 01000

Ø  SAR = 01010    (Third Cycle)

V_DAC = 0+0.25+0+Vref/2^4 = 0+0.25+0+1/16 =0.3125  , Vin < V_DAC  , SAR bit 2  is reset , 01000

The answer , after 3 clock cycle the content of SAR is 01000

Sequential Circuits - MCQ

1. How many flip flop will be complemented in a 10 bit binary up counter to reach the next count after the count 1001100111.

Answer : 

Add 1 to the value and see the number of bits get toggled to obtain the number of flip flop need to be complemented in a binary up counter to reach the next count

 4 bits are toggled to obtain next count . So, 4 flip flops will be complemented.

2. A binary ripple counter uses flip-flops that trigger on the positive edge of the clock. What will be the count if the normal outputs of the flip-flops are connected to the clock input of the next stage.

      Answer : Positive Triggering  : 0 à1 , flip flop toggles when the clock goes 0 à1

A count down counter

3.   The contents of a four-bit register are initially 0110. The register is shifted six times  to the right with the serial input being 1011100 ( inputs are applied from right to left ). What is the content of the register after each shift ?

     Answer : 

      Content of the register : 0110

Input : 1011100

Output : 0011 ; 0001; 1000 ; 1100; 1111; 0111; 1011

4. The characteristic equation of SR flip flop is Q(n+1) = S+R’Qn

5.  A 4 bit shift register circuit configured for right shift operation ( Din àA, AàB, B à C, CàD) as shown. If present state of the shift register is ABCD = 1101, the number of the clock cycles required to reach the state ABCD 0100 is 

Answer : 

Present state  : 1101 ,

Din is A ⊕ D

output : 0100

6.  The race around condition occurs in a J-K flip flop when

Answer :

       JK flipflop has three inputs and two outputs. Outputs are complementary to each other.
 when J =K = 0 and clk = 1; output of AND gates will be 0; when any one input of NOR gate is 0 output of NOR gate will be complement of other input, so output remains as previous output.

 when J =0  K =1 and clk = 1; output of AND gate connected to K will be Q and corresponding NOR gate output will be 0; which RESETs the flipflop.

 when J =1  K = 0 and clk = 1; output of AND gate connected to j will be Q' and corresponding NOR gate output will be 0; which the SETs the flipflop.

 when J =1  K = 1 and clk = 1; Q output will toggle as long as CLK is high. Thus the output will be unstable creating a race-around problem with  this basic JK circuit.

      7.    The minimum number of flip flops required to design a MOD-10 ripple counter is  4

Answer : MOD 10 à 10 binary value 1010 so 4 flip flops.

8. In general ,a sequential logic circuit consist of flip-flops and combinational circuits.

Answer : A sequential logic circuit consists of a combinational circuit and memory elements that form a feedback system. Flip flop used as memory element.

9.  While converting  JK flip-flop to D Flip-flop, instead of connecting an invertor between J and K inputs a buffer has been connected . The resulting circuit will be  T Flip-flop

10. Between a Latch and Flip-flop which one has higher possibility of getting input data noise propagated to it output. 

Answer : Latch act faster than the flip-flop as it react immediately once the input change.

11.  A Finite State Machine (FSM) with one input (X) and one output (Z) is defined by the state diagram below . Assume FSM starts with the state A. Given is the following sequence of input (X) values. 

X : 10010110101010. 

What state is the FSM in at the end of the above sequence ? What input can be detected by this ?

Answer : State C , Sequence detected 101

12. What is the function implemented by the circuit given below ? Assume the signal w is driven by square wave signal.

Answer :

When both flip-flops are cleared, their outputs are Q0 = Q1 = 0. After the Clear input goes high, each pulse on the w input will cause a change in the flip-flops as indicated in Figure. Note that the figure shows the state of the signals after the changes caused by the rising edge of a pulse have taken place. In consecutive time intervals the values of Q1Q0 are 00, 01, 10, 00, 01, and so on. Therefore, the circuit generates the counting sequence: 0, 1, 2, 0, 1, and so on. Hence, the circuit is a modulo-3 counter.

13.What would be the number of flip-flops required to design mod-10 ring counter and mod-10 Johnson counter respectively?

Answer :

To design MOD-N ring counter , N number of flip-flop is needed., so, 10 flip-flops are needed.

The MOD of the Johnson counter is 2n if n flip-flops are used.  So, if MOD-10 counter is to be designed 10 can be written as 2n = 2X5, 5 flip-flop is needed.

14.What is the modulus of the counter circuit shown below ?

Answer : MOD – 10 counter

15.What logic block should be placed at the point X so that circuit acts as a MOD-7 counter?

Answer : 

X should be replaced by Three input NAND gate , so that the ripple counter  can be  reset for 7 (111).